Updates PHOTO_V pin to use pin P0.29 from both modules

- Updated schematic
- Updated pcb layout
This commit is contained in:
rbaron 2021-09-11 10:57:54 +02:00
parent 9c6fdfacfc
commit 0e5f8b8f9d
3 changed files with 498 additions and 443 deletions

File diff suppressed because it is too large Load diff

View file

@ -1,7 +1,17 @@
update=27/05/2021 11:02:09
update=2021 September 11, Saturday 10:57:37
last_client=kicad
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=./
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@ -12,7 +22,7 @@ AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinTrackWidth=0.15
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
@ -229,13 +239,3 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=./
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

View file

@ -800,7 +800,6 @@ Wire Wire Line
Wire Wire Line
1900 1400 2025 1400
NoConn ~ 2025 1600
NoConn ~ 2025 1800
NoConn ~ 2025 1900
NoConn ~ 2025 2000
NoConn ~ 2025 2700
@ -879,9 +878,7 @@ Wire Notes Line
8700 4025 8700 5775
Wire Notes Line
8700 5775 11050 5775
Wire Wire Line
2025 1100 1900 1100
Text Label 1900 1100 2 50 ~ 0
Text Label 1875 1800 2 50 ~ 0
PHOTO_V
Text Label 9300 4750 2 50 ~ 0
PHOTO_V
@ -906,4 +903,7 @@ Wire Wire Line
Connection ~ 9950 4750
Wire Wire Line
9300 4750 9400 4750
Wire Wire Line
1875 1800 2025 1800
NoConn ~ 2025 1100
$EndSCHEMATC